1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a semiconductor memory device which drives a plurality of sub word line drivers using output signals (GWLB,SWLE) of a row decoder so as to efficiently control a column selection signal.
2. Discussion of the Related Art
A related art semiconductor memory device will be described below with reference to the accompanying drawings.
FIG. 1 shows the configuration of a related art semiconductor memory device.
The related art semiconductor memory device, on the whole, includes a memory cell array, a row decoder and sub word line driver section, and a column selection driver section.
The row decoder and sub word line driver section includes a plurality of sub word line driver (SWD) sections 3 for driving memory cells in memory cell array sections 4, a row decoder 2 for generating a plurality of global word line bar (GWLb) signals and global word line (GWL) signals in the SWD sections 3, the GWLb signals and GWL signals being decoded by the most significant bit (MSB) address, and a sub word line enable section 1 which generates a sub word line enable (SWLE) selection signal decoded by the least significant bit (LSB) address.
The column selection driver section includes a plurality of bit line sensing amplifier arrays 5 connected to each of the memory cell arrays 4, for sensing data, a plurality of column decoders 6 for decoding input column address, a plurality of column selection lines 7 for serially connecting each of the column decoders 6 with each of the bit line sensing amplifier arrays 5.
Here, each of the bit line sensing amplifier arrays 5 includes a plurality of sensing amplifiers 5a which are respectively connected to a bit line and a bit bar line. The bit line sensing amplifier arrays 5 include a sensing amplifier equalization and precharge enable section(EQ/PCH). Each of the bit lines and bit bar lines is connected to the cells in the memory cell array sections 4.
Y-gates 5b are connected to the bit lines and bit bar lines connected to each of the bit line sensing amplifiers 5a, so that the bit lines and bit bar lines are selected depending on turning on of the Y-gate 5b. Turning on/off of the Y-gate 5b is controlled by the corresponding column decoder 6. That is, among a plurality of column decoders 6, if a column decoder 6 corresponding to input address is selected, a column selection line 7 connected to the selected column decoder 6 is selected, so that Y-gate 5b connected to the selected column selection line 7 is turned on.
In this way, data in the memory cell is amplified by the sensing amplifiers, and then transmitted to a data line and a data bar line through selected bit lines and bit bar lines.
The operation of the related art semiconductor memory device will be described below by focusing on a row decoder and sub word line driver section.
FIG. 2a is a schematic view of a unit sub word line driver of the related art semiconductor memory device, and FIG. 2b is a timing chart showing the operation of a row decoder and the unit sub word line driver of the related art semiconductor memory device.
The sub word line driver includes a PMOS transistor P20 whose gate receives the GWLb signal from the row decoder 2, and an NMOS transistor N22, and an NMOS transistor N21 whose source is connected to the SWL. The drains of the PMOS transistor P20 and the NMOS transistor N22 are connected to the SWL. The SWLE signal generated by SWLE section 1 is applied to the source of the PMOS transistor P20 and the drain of the NMOS transistor N21, and the GWL signal generated by row decoder 2 is applied to the gate of the NMOS transistor N21.
In the row decoder and the unit sub word line driver of the related art semiconductor memory device, all the GWL signals and SWLE signals are in a state of low voltage during a period of t1, as shown in FIG. 2b. And, GWLb signal is in a state of boosted voltage. Accordingly, the PMOS transistor P20 which is connected to the GWLb line is turned off but the NMOS transistor N22 is turned on, thereby maintaining the SWL in a state of low voltage. At this time, the NMOS transistor N21 is turned off state.
During a period of time t2, the SWLE signal decoded by the LSB address has boosted voltage, the GWLb signal decoded by the MSB address has low voltage and the GWL signal has high voltage. Consequently, the PMOS transistor P20 and the NMOS transistor N21 are turned on while the NMOS transistor N22 is turned off, so that the boosted voltage of the SWLE signal is transmitted to the SWL, thereby generating the SWL signal.
The operation of the column selection driver of the related art semiconductor memory device will be described below.
FIG. 3 is a timing chart showing the operation of a column decoder and a bit line sensing amplifier array section of the related art semiconductor memory device. Among a plurality of column decoders 6 each connected to column selection lines 7, a column decoder 6 corresponding to input addresses(PYij, PYkl, PYmn, PYxy) is selected. If the column decoder 6 is selected, the column selection line 7 which is connected to the selected column decoder 6 is activated. Thus, Y-gate 5b connected to the activated column selection line 7 is turned on, so that data of a corresponding memory cell in the memory cell array section 4 is transmitted to the sensing amplifier 5a through the bit line and bit bar line. The sensing amplifier 5a senses and amplifies the data input through the bit line and bit bar line, and then outputs it through the data line and data bar line.
In the column selection driver of the related art semiconductor memory device, the sensing amplifier arrays 5 are commonly connected to the column selection lines 7, to write data in the memory cell array 4 and read data of the memory cell array 4 through the data line and data bar line.
However, the above-described related art semiconductor memory device has the following problems.
First, in the row decoder section, the GWL signal and GWLb signal which control a plurality of sub word lines are generated by the row decoder and connected to four SWDs. This means that there are two metal lines, GWLb and GWL signal lines, every four polysilicon word line. This causes defects in the word line during the fabrication process due to shortage of design rule margin. Furthermore, coupling noise is generated between the word lines and between the word line and the bit line, deteriorating the performance of memory chip.
Further, in the column selection driver, since the bit line sensing amplifier arrays are commonly connected to the column selection lines, if a random column selection line is activated, all the bit line sensing amplifier arrays connected to the column selection line are activated. This increases power consumption unnecessarily. Moreover, when the selected bit line sensing amplifier array transmits the corresponding data to the data line and data bar line, unselected bit line sensing amplifier array also transmits the data to the corresponding data line and data bar line. Accordingly, bit line precharge voltage and data line precharge voltage come into collision with each other in the unselected bit line sensing amplifier array, thereby increasing unnecessary power consumption. The larger the memory capacity is, the more power consumption increases. Also, loading of the column selection line is increased to reduce the processing speed. In order to prevent the precessing speed from being reduced, there is suggested a method of increasing the size of the driver. However, the more the size of the driver increases, the more power consumption increases.